Most home-centric electronics products demand low power at cost aggressive prices. Given that, the processor which is selected for many designs is undergoing a major transformation. The force behind this fundamental change is known as RISC-V (Reduced Instruction Set Computing – 5th iteration). RISC-V—pronounced “risk five”—is an open, free ISA (instruction set architecture).
What does that mean? An ISA includes the available set of commands that a processor has to execute. With RISC-V, all of these instructions are open and available for anyone to use. This is very different from today’s leading processor architectures, where the chip makers solely dictate what their processors support and what they do not.
Efficient, Purpose-Built Processors
RISC-V enables any silicon chip company to design their own processor and customize it optimally for their application. This configurability is driving increasing popularity and is unleashing a new level of innovation. RISC-V leverages the power of an open standard for a broad range of purpose-built processor requirements.
Similar to the growth the advent of the Linux® operating system has precipitated for software, RISC-V has the potential to disrupt hardware in the same way. This is a primary reason why there are more than 235 organization members in the RISC-V Foundation.
As stated, the RISC-V ISA is completely open for all to use. By exposing all the instructions, various types of processor implementations are possible. RISC-V also allows for an option to implement custom instructions. This enables far more customization than is available from off-the-shelf processor alternatives.
RISC-V, therefore, is an ideal platform to create purpose-built solutions. For example, a RISC-V processor with custom instructions to implement vector multiplication could improve the performance of a machine-learning application.
RISC-V: Already in Google Pixel Smartphones
It is still early in the maturity of RISC-V, but there are already some implementations where the benefits can be seen. Recently, Google announced they were using RISC-V cores for the Image Processing Unit (IPU) that goes into their Pixel brand of smartphones.
Ofer Schacham, senior staff engineer at Google, discussed benefits of their RISC-V implementation in a blog post. In the post, Schacham stated: “Pixel Visual Core is the Google-designed Image Processing Unit (IPU)—a fully programmable, domain-specific processor designed from scratch to deliver maximum performance at low power.”
These performance and power benefits for real-world applications can be substantial. By way of example, Google says their HDR+ feature on the Pixel Visual Core IPU gains a 5X speed boost while consuming less than one-tenth of the energy that would be used on the main processor.
RISC-V: On Your Wrist
Another example of a company which is leveraging the simplicity of the reduced ISA is Huami. They have introduced the Amazfit smart watch.
During development of this RISC-V based device, Huami optimized the implementation of the processor for lower power and cost. Only the required interfaces and peripherals that the watch required were incorporated into the design. The result is a purpose-built, highly-efficient solution: The Amazfit watch is able to operate for approximately 5 days of use on a single charge.
Coming Soon to Your Home
While RISC-V continues to gain traction, there are gaps in the tools and software. Certainly, this is being addressed, but the ecosystem takes time to develop. This may limit how and where RISC-V is used in designs, at least in the short-term. But there are enough market incentives that will make this a compelling technology to watch in coming years.
Given that the RISC-V ISA provides simplicity, configurability, and openness, it will find its way into a growing number of devices. RISC-V gives designers an entirely new processor paradigm from which to reach beyond the constraints of the established processor status quo and push the boundaries of innovation. You can look for more products based on RISC-V coming to your connected home soon.
Ted Marena is Director, RISC-V Ecosystem, at Western Digital, where he is responsible for evangelizing RISC-V, accelerating the build out of the RISC-V ecosystem, and marketing machine learning solutions. Ted was elected Marketing Chair for the RISC-V Foundation in 2016, has over 25 years of experience in electronics, and excels at business development, marketing, and revenue growth.